1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system.
2. Description of the Related Art
A memory device includes a memory cell area, having a plurality of memory banks, and peripheral circuits for controlling data input/output of the memory cell area. A memory bank is a group of memory cells for storing data, and the memory cells are arranged in a plurality of rows and columns to form a cell array. An address is assigned to each of the rows and columns.
In a memory device, a data access operation in one memory bank includes activating a word line corresponding to an applied row address, reading or writing data from or to a memory cell, which is coupled to a bit line corresponding to an applied column address, among the memory cells coupled to the activated word lines and precharging the word line. As such, the operation of the memory cell area (e.g., a memory bank) may be classified into a row operation for controlling word lines and a column operation for controlling bit lines.
FIG. 1 is a block diagram illustrating a conventional memory device.
Referring to FIG. 1, the memory device may include a command input unit 110, an address input unit 120, a command decoder 130, a bank selection unit 140, and a memory cell area 150. The memory cell area 150 may include eight memory banks BANK0 to BANK7.
The command input unit 110 may receive a plurality of command signals CMDs transmitted from an external source, and the address input unit 120 may receive a plurality of address signals ADDS transmitted from an external source. The command input unit 110 and the address input unit 120 may receive the command signals CMDs and the address signals ADDs in synchronization with a clock CLK. The address signals ADDs may include bank addresses BADDs for selecting memory banks, row address RADDs for selecting rows (i.e., word lines), or column addresses CADDs for selecting columns (i.e., bit lines). Each of the bank addresses BADDs, the row addresses RADDs, and the column addresses CADDs may include multiple bits.
The command decoder 130 may decode the command signals CMDs received through the command input unit 110, and enable an internal command ICMD based on a combination of the command signals CMDs. The internal command ICMD corresponding to a row operation may include an activate command, a precharge command, a refresh command and the like, and the internal command ICMD corresponding to a column operation may include a read command, a write command and the like. The bank selection unit 140 may transmit the internal command ICMD generated by the command decoder 130 to a memory bank corresponding to an inputted bank address BADD.
The first to eighth memory banks BANK0 to BANK7 of the memory cell area 150 may receive first to eighth internal commands ICMD_B<0:7>, respectively, and perform a row operation or a column operation using the row addresses RADDs and the column addresses CADDs.
The specifications, which must be obeyed by a memory device such as DRAM may include tRAS (i.e., a time required until one memory bank is precharged after the memory bank is activated), tRP (i.e., a time required until one memory bank is activated after the memory bank is precharged), tRRD (RAS to RAS Delay), tRCD (RAS to CAS Delay) and the like. All of the times may be set on the basis of a clock.
The memory device of FIG. 1 has only one channel for receiving command signals CMDs and one channel for receiving address signals ADDS. Thus, even though the memory banks BANK0 to BANK7 may be controlled independently within the memory device, the memory device has a limitation in receiving command signals CMDs or address signals ADDs for operating two or more memory banks at once. Furthermore, since the command input unit 110 and the address input unit 120 receive command signals CMDs and address signals ADDS at a first rising edge of a clock CLK, respectively, both the command input unit 110 and the address input unit 120 must have a plurality of input pads corresponding to the maximum number of signals that may be inputted simultaneously. Thus, the operation speed of the memory device may be lowered, and the size of the memory package may be increased.